This invention relates to a synchronous counter circuit, and more specifically to a synchronous counter circuit having a plurality of cascade-connected counters, which is suitable for use in a gate array and a standard cell.
The gate array and the standard cell make up a large logic function circuit using a micro cell library. A synchronous counter circuit is known as the logic function circuit. The synchronous counter circuit comprises a plurality of cascade-connected counters. However, the synchronous counter circuit tends to malfunction when the difference in time between an enable signal output from the counter provided at the preceding stage and a clock signal becomes small.